This invention relates to compression of digital waveform data for viewing in a logic analyzer, and more particularly to an arrangement that provides such compression in much less time than is possible in apparatus according to the prior art.
A modern logic analyzer may be implemented on electronic circuit boards (ECBs), or cards, mounted in a card cage. One of these cards typically is the controller card for controlling the logic analyzer system, and is in reality a PC on a card. The controller on this card is usually a relatively powerful PC compute engine, such as an Intel 266 MMX, or other suitable microprocessor. The other cards in the logic analyzer system are acquisition modules for acquiring and storing digital data for evaluation and display. Clock, control, and data signals are coupled between each of the ECBs by means of a backplane.
Memory depth has been growing steadily since the introduction of logic analyzers. Consider a modern logic analyzer having a memory depth of 400 Mbytes of data. Such a memory can be visualized as an array of memory locations 16 million rows long, and 196 bits wide (e.g. 136 bits of digital data, 52 time stamp bits, and 8 flag bits). This data must be compressed for display on a display screen. Recall that a display pixel is the smallest picture element capable of being illuminated on a display screen. A typical display screen has about 800 display pixels per horizontal line. With such a logic analyzer and display screen, and depending on the particular settings chosen, there could be any number from zero to 1 million samples per pixel.
Heretofore, logic analyzer waveform generation calculations have been performed in software, and the time required to perform these sequential operations has posed a limitation on the overall performance of the logic analyzers using that approach. Simply improving the PC compute engine does not address all limitations of the system. One such limitation has been the necessity of moving substantially all of the data across the backplane for processing by the controller PC. Unfortunately, state-of-the-art processors can have no effect on backplane or bus interfaces and standards, because those interfaces and standards exhibit inherent data limits. One might think that a solution would be to put a powerful PC on each acquisition module to reduce the amount of data transfer by performing all of the data evaluation on the acquisition module. However, this approach does not solve the problem adequately for several reasons. First, a powerful PC would still be required to control all of the acquisition modules, and to control display of the processed data. Second, even if the main PC controller were to be duplicated on each acquisition module, the total time required to evaluate the samples per pixel would not be reduced to a significant degree due to the limitations of performing data evaluation in software.
Note that the word xe2x80x9cpixelxe2x80x9d also has a secondary meaning which is a term of art in the logic analyzer field. Hereinafter, when the term xe2x80x9cpixelxe2x80x9d is used it actually refers to a variable height column of display pixels. One must evaluate the sample data to determine whether the pixel associated with that data should be drawn as a logic one (i.e., illuminate the top most display pixel in its column), a logic zero (i.e., illuminate the bottom most display pixel in its column), or as an edge (i.e., illuminate all display pixels in their column), indicating a change of state from a low to a high, or a high to a low.
In prior art logic analyzers, in order to evaluate the data, software running on the main PC would determine the time span of the pixel on the basis of the user""s selection of a horizontal time scale. The software would determine which samples fell within the time span of each pixel. The software processes would begin with the first sample and check every sample in every channel within the pixel time span to determine the state of each sample during each sub-interval, i.e., whether it was always xe2x80x9chixe2x80x9d, always xe2x80x9clowxe2x80x9d, or made a xe2x80x9ctransitionxe2x80x9d from one state to the other. This process would also be informed of any applicable violation data saved in connection with any channel during one of the sub-intervals comprising the timeslice. Violation data, which is usually determined by hardware, includes glitches or an improper setup or hold time. From the foregoing information, the software would determine how to represent each channel during that timeslice in the logic analyzer display. This whole procedure is then repeated for every pixel column (timeslice) across the screen. Thus, this overall process requires substantially all of the data to be moved across the backplane to the PC card, requires a huge number of read and compare operations in the PC, and necessarily consumes a large amount of time, typically on the order of four to five minutes.
What is needed is apparatus capable of performing the evaluation of up to one million samples per pixel in a much shorter time.
In accordance with the present invention, hardware circuitry is loaded with memory address related data, and is used to perform waveform compression more rapidly than could be done by software alone. Compression entails evaluating the data from a number of acquired data points on one channel over a period of time to determine if the data changed state during the period of time. The resulting highly compressed data is summarized to produce pixel illumination data. The pixel illumination data, and not the raw data, is conveyed to a controller for display.